This invention relates to a method for manufacturing a semiconductor device and, in particular, a method for manufacturing a semiconductor device, having a multi-layered interconnect structure, on an insulating substrate.
A SOS (Silicon On Sapphire) structure is conventionally known as a semiconductor structure having an insulating material as a substrate. The SOS structure is fabricated by epitaxially growing single crystalline silicon layer 42, as a semiconductive layer, on single crystalline sapphire substrate 41, and forming semiconductor elements on the silicon layer.
In the fabrication of the aforementioned SOS structure, several dry steps are performed in the process of forming semiconductor elements. The dry process includes, for example, a dry-etching step using plasma, a plasma CVD (Chemical Vapor Deposition) step, and so on.
The dry process, as opposed to a wet process using various types of acid or alkali solutions, comprises depositing and forming a thin film, through utilizing dissociated and ionized gaseous plasma resulting from a discharge occurring between opposite electrodes. Such a dry process contains an ion etching step comprising ionizing an inactive gas, and accelerating the ionized gas atoms, using a high voltage to cause them to collide with each other (i.e., utilizing physical energy); a plasma etching step utilizing a chemical reaction of active gas under a plasma phase; and an RIE (Reactive Ion Etching) step utilizing a combination of chemical and physical reactions.
Even in the aforementioned plasma CVD step, a thick film is deposited through utilizing the reaction of gas atoms under a plasma phase.
As a semiconductor device manufactured by using more dry steps, a semiconductor device of a type having, for example, a double-layered interconnect aluminum structure, is known.
In the formation of the aforementioned double-layered aluminum structure, an insulation interlayer should be planarized in the formation of a reliable interconnect line. In order to achieve this, an etchback method is known in the art. Stated in more detail, a layer which is formed during the formation of a first interconnect aluminum layer, is etched back to provide a planarized insulation interlayer. The process which manufactures semiconductor devices will now be explained below, with reference to FIGS. 2A to 2C.
Subsequent to the formation of first interconnect aluminum layer 51, insulation interlayer 52 is formed by means of a plasma CVD step, and resist 53 is spin-coated onto the surface of the resultant structure (see FIG. 2A). Then, an etch-back step is carried out, by using an RIE process such that the same etching rate is used with respect to the resist and the plasma CVD film (see FIG. 2B). Next, SiO.sub.2 film 54 is formed by use of the plasma CVD step, followed by the formation of second interconnect aluminum layer 55 (see FIG. 2C).
In this way, second interconnect aluminum layer 55 is formed over planarized first interconnect aluminum layer 51.
As has been set out above, the etch-back method is necessary for the planarization of insulation interlayer 52, but a problem occurs in that a nonuniformity is liable to occur in the film thickness formed, as well as in the amount of etching over the wafer surface. As a result, an adequate degree of insulation cannot be assured between first and second interconnect aluminum layers 51 and 55 at the thinner portion of the insulation interlayer formed by the CVD method, thus shorting may occur at the insulation interlayer. At the thicker portion of the insulation interlayer, on the other hand, no adequate contact hole is formed, by the reactive ion etching, for a satisfactory connection between first and second interconnect aluminum layers 51 and 55.
These problems present an obstacle to the mass manufacture of semiconductor devices, with a stable yield, with necessary working applied.
It is considered that the aforementioned nonuniformity arises due to the fact that the electrochemical reaction of the wafer in the plasma gas atmosphere varies depending upon the state of the wafer. Where, for example, the SOS structure is subjected to the plasma CVD step, a high-frequency voltage is applied to a carbon sheet in the gaseous atmosphere, to thereby create a gaseous plasma, so that a plasma CVD film may be formed. Since, in the SOS structure, for example, sapphire is used as the insulating substrate, a potential on the wafer is never made uniform upon the application of a high-frequency voltage to the carbon sheet, thus causing an unstable state to be induced from the electrical standpoint. As a result, an uneven deposition layer is formed and, moreover, the depth of etching varies during the etching step, such as the RIE step.